DVLab · Design Verification Lab, NTUEE

DVLab (Design Verification Lab) at NTU EE, led by Prof. Chung-Yang (Ric) Huang. Research on formal verification, quantum circuit synthesis and optimization, and EDA.

DVLab group photo during a hiking activity

Lab hiking trip

Meet the Team Publications Courses Awards

Highlights

Research Team

Led by Prof. Chung-Yang (Ric) Huang, our members span Master's, PhD, and undergraduate researchers working on formal verification, quantum computing, and EDA.

Research Outputs

The lab has been recognized at ICCAD CAD Contest, DAC, DATE, and QCE, and continuously publishes high-quality research.

Recruitment & Collaboration

We welcome students interested in verification, quantum circuits, and EDA, as well as academic and industrial collaboration.