Arvind Singh Rathore

About

I am a master's student at the National Taiwan University, Graduate Institute of Electronics (NTU GIEE) Design Verification Lab supervised by Prof. Chung-Yang (Ric) Huang. At DVlab, I am focusing on CPU verification. I have had the priviledge to work under Prof. Ric at NTU and I am eager to learn a lot from him owing to his vast experience in the SoC Verification domain. In the summer of 2022, I interned at TSMC's 3D IC Design Methodology team at their Headquarters in Hsinchu. I was responsible for building a SoIC QC testcase all the way from RTL to GDSII for checking the quality of n7 APR tec