邱浤竣

簡介

I am a master's student at the National Taiwan University (NTU) Design Verification Lab supervised by Prof. Chung-Yang (Ric) Huang. I am adept at the verification field in EDA.；I received my Bachelor's degree in Computer Science from YZU in 2022, and I am studying for the master degree in Integrated Circuit Design and Automation, NTU. I have had the privilege to work with Prof. Chung-Yang (Ric) Huang at NTU.