論文
本頁收錄黃鐘揚教授任職臺大期間的論文，包含跨實驗室合作成果。
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Ultra-Low Logical Depth Fault-Tolerant Quantum Circuit Synthesis via Lattice Surgery
DATE 2026
Unified Pauli-Rotation Synthesis for Relieving CX-Count Overhead in Tableau-Based Quantum Circuit Optimization Flow
DATE 2026
A Lazy Resynthesis Approach for Simultaneous T Gate and Two-Qubit Gate Optimization of Quantum Circuits
IEEE QCE 2025
Efficient Rectification Signal Validation for Optimal Functional ECO Patch Generation
DAC 2025
Qsyn: A Developer-Friendly Quantum Circuit Synthesis Framework for NISQ Era and Beyond
IEEE QCE 2024
Robust Qubit Mapping Algorithm via Double-Source Optimal Routing on Large Quantum Circuits
ACM Trans. on Quantum Computing 2024
Compatible Equivalence Checking of X-Valued Circuits
ICCAD 2021
Joint Sequence Learning and Cross-Modality Convolution for 3D Biomedical Segmentation
CVPR 2017
Automatic abstraction refinement of TR for PDR
ASP-DAC 2016
A Counterexample-Guided Interpolant Generation Algorithm for SAT-Based Model Checking
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2014
A High-Throughput and Arbitrary-Distribution Pattern Generator for the Constrained Random Verification
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2014
Adaptive interpolation-based model checking
ASP-DAC 2014
A counterexample-guided interpolant generation algorithm for SAT-based model checking
DAC 2013
A robust constraint solving framework for multiple constraint sets in constrained random verification
DAC 2013
An Ultrasynchronization Checking Method With Trace-Driven Simulation for Fast and Accurate MPSoC Virtual Platform Simulation
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2013
Conquering the scheduling alternative explosion problem of SystemC symbolic simulation
ICCAD 2013
Match and Replace: A Functional ECO Engine for Multierror Circuit Rectification
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2013
A robust general constrained random pattern generator for constraints with variable ordering
ICCAD 2012
A semi-formal min-cost buffer insertion technique considering multi-mode multi-corner timing constraints
ASP-DAC 2012
Multi-patch generation for multi-error logic rectification by interpolation with cofactor reduction
DATE 2012
QuteRTL: Towards an Open Source Framework for RTL Design Synthesis and Verification
TACAS 2012
Symbolic model checking on SystemC designs
DAC 2012
A robust ECO engine by resource-constraint-aware technology mapping and incremental routing optimization
ASP-DAC 2011
Interpolation-based incremental ECO synthesis for multi-error logic rectification
DAC 2011
Match and replace - A functional ECO engine for multi-error circuit rectification
ICCAD 2011
Property-specific sequential invariant extraction for SAT-based unbounded model checking
ICCAD 2011
SoC HW/SW verification and validation
ASP-DAC 2011
Speeding Up MPSoC virtual platform simulation by Ultra Synchronization Checking Method
DATE 2011
Toward an extremely-high-throughput and even-distribution pattern generator for the constrained random simulation techniques
ICCAD 2011
Using SAT-based Craig interpolation to enlarge clock gating functions
DAC 2011
A robust functional ECO engine by SAT proof minimization and interpolation techniques
ICCAD 2010
A unified multi-corner multi-mode static timing analysis engine
ASP-DAC 2010
Automatic constraint generation for guided random simulation
ASP-DAC 2010
Formal deadlock checking on high-level SystemC designs
ICCAD 2010
Speeding up SoC virtual platform simulation by data-dependency-aware synchronization and scheduling
ASP-DAC 2010
To SAT or Not to SAT: Scalable Exploration of Functional Dependency
IEEE Trans. Computers 2010
A false-path aware formal static timing analyzer considering simultaneous input transitions
DAC 2009
Interpolant generation without constructing resolution graph
ICCAD 2009
SAT-controlled redundancy addition and removal: a novel circuit restructuring technique
ASP-DAC 2009
Improving Constant-Coefficient Multiplier Verification by Partial Product Identification
DATE 2008
QuteIP: An IP qualification framework for System on Chip
SoCC 2007
QuteSAT: a robust circuit-based SAT solver for complex circuit structure
DATE 2007
Scalable exploration of functional dependency by interpolation and incremental SAT solving
ICCAD 2007